Part Average testing is a statistical screening technique first published by the Automotive Electronics Council (AEC) to improve automotive electronics reliability. The AEC was originally established by Chrysler, Ford, and GM for the purpose of defining common part-qualification and quality-system standards. After analyzing industry quality and reliability statistics, the AEC published a number of recommendations and guidelines for component suppliers.
In 1997 the AEC released “Guidelines for Part Average Testing (provides guidelines for using statistical techniques and extended operating conditions to establish part test limits; this approach could be used to provide “Known Good Die)”in document AEC-Q001. The last revision was released in Dec 2011 as AEC-Q001 Rev-D. http://www.aecouncil.com/Documents/AEC_Q001_Rev_D.pdf.
In addition, the AEC released “Guidelines for Statistical Yield Analysis (provides guidelines for using statistical techniques to detect and remove abnormal lots of integrated circuits)”as document AEC – Q002 Rev – B:
Adherence to these guidelines and techniques is often contractually required of semiconductor suppliers by automotive, medical and other high reliability application OEM’s.
The Static PAT Limit Procedure
An overview of the PAT procedure is:
- Sample 30 random parts from ≥6 lots, (5 zonally different die from wafer lots). Include characterization lots in early
- Establish a “robust mean” (µ) for each test setting µ= the statistical median and calculate a “robust sigma” as σ = (Q3 – Q1)/1.35 from the Quartile (Q3 and Q1) measurements.
- Define Static PAT Limits =µ ± 6σ
- If distributions are not Gaussian (“Normal”) in 3) use “defendable” techniques to flag outliers exhibiting the same probability (about 1 in 506.8 Million).
- The Static PAT Limits are updated every 6 months or 8 wafer lots whichever comes first.
Dynamic PAT Limits
- Dynamic PAT Limits are calculated the same as Static PAT Limits but use a “rolling” sample of “Passed” parts from the current lot (or wafer) to establish the mean and standard deviation(or appropriate non-Gaussian limit). In this case, the results from “Passed” parts are re-analyzed after the lot (or wafer) is complete to determine if they fall outside of the Dynamic PAT Limits = µ ± 6σ using the tighter lot or wafer distribution. If they are “outliers” they are rejected despite passing the original USL, LSL test.
Dynamic PAT Limits Special Cases
For devices where measurements are not parametric (pass/fail) or the devices cannot be indexed (e.g. tracked using serial id’s), Dynamic PAT requires re-testing parts to check for outliers. The AEC does accommodate using Static Limits for 500 or 1000 units which, if passed, form the sample for calculating the tighter Dynamic PAT Limits for subsequent devices. This avoids retesting the parts.
Managing a contractual obligation for PAT is challenging since devices can pass the production test and afterwards be deemed an outlier and scrapped. Since these limits need to be recalculated (in some cases on a wafer to wafer basis) a sophisticated Yield Management System like yieldWerx Enterprise simplifies ensuring compliance. For very high volumes, a YMS system becomes a necessity.