Synopsis:
This module supports a variety of outlier detection techniques which require using data from a wafer lot, single wafer, or localized neighborhood of the die to make the pass/fail determination. Product and quality engineers use these techniques to reach quality and reliability product targets. Both real-time and post-test applications of these limits can be supported.
Description:
In high-volume manufacturing achieving 100% detection of all defective products, in particular, those subjected to latent defects (reliability-related failures) is a high bar. Over the last three decades product engineers, quality engineers, and statisticians have jointly developed test detection techniques that go beyond a simple pass/fail test results of the device under test (DUT). These techniques detect DUTs that later fail at final test, after burn-in, or in a customer system. Even though the DUT passed all parametric tests, the DUT looks different from the others.
Engineers require a toolbox of techniques that can be applied with wafer test data to make these outlier detection assessments. The following list of algorithms are supported:
- Static Part Average Testing (SPAT)
- Dynamic Part Average Testing (DPAT)
- Good Die in Bad Neighborhood (GDBN)
- GDBN-Z
- Multi Variant Analysis
- Non-Gaussian Data Distribution Detection
The Automotive Electronic Council has codified PAT as a requirement electronics supplier in Q001 Rev-D guidelines. When setting limits based upon a parametric distribution the reality is those limits may shift due to process shifts. For example, making fab process changes to create faster CMOS transistors inevitably increases static leakage used for IDDQ testing. The ability to monitor parametric shifts with other analysis tools (Statistical Process Control) and then implement a change to the limits can be easily done with this module’s PAT policy editor.
Part Average Test limits lend themselves to real-time interaction with the tester. This permits a finer granularity of application and the ability to modify the limits at the lot level, wafer level, or reticle site. Engineers name this finer granularity Dynamic PAT. Engineers can calculate DPAT limits on sample size defined by the end-user. They can also program this module to recalculate limits after N number of units have been tested as required.
To consider changing PAT limits or applying other outlier techniques, engineers simulate the impact on pass/fail fallout. No need to write custom scripts for every new product or possible outlier technique. Using available product test results data engineers rapidly explore different detection algorithms and select the one that provides the balance of detection and yield loss.
Where applied:
- Wafer Test
- Assembly Map Generation
- Final Test