Abstract: In this webinar, we will provide practical steps for scaling advanced semiconductor devices in high-complexity environments, including silicon photonics, Co-Packaged Optics (CPO), and advanced packaging. Traditional analytics approaches struggle with multi-domain test flows, serialized module assembly, and the coupling between process, packaging, and system-level performance. The session will present strategies for unifying heterogeneous manufacturing data, managing multi-stage traceability, and correlating wafer-level characterization with optical, thermal, and system-level behavior, along with real-world implementation pitfalls and architectural tradeoffs.
Access this Webinar to Learn:
* Ingesting and normalizing multi-source data across WAT/PCM, OWAT, EWAT, spectral and laser test, defect/metrology inspection, module BOM, assembly, burn-in, and final test
* Correlating device-level parametrics with process, packaging, and module performance outcomes
* Building a digital thread spanning Design→ Mfg→ Wafer → Die → Module → System and using AI-assisted analytics to accelerate root-case discovery
Meet the Speaker can be the same as the PAT++ one.