Conducting Yield Analysis for Semiconductor Manufacturing

Semiconductor manufacturing is a complex process that comprises series of stages. During these stages, fully functional Integrated Circuits (ICs) are produced from raw materials such as bare silicon wafers. The four main stages of manufacturing are:

• Wafer Fabrication
• Probe Testing
• Packaging
• Final Testing

In the wafer fabrication process the structure of integrated circuits is sketched on the wafers and each of them is tested with the help of a probe in the probe testing stage. Once tested, the wafers are then cut (diced) into many pieces, with each piece containing a copy of a fully functional IC, these individual pieces are called a die. The dies that pass the test stage are packaged and sent for a final yield test before shipping. Faults or processing issues that may occur during any of these stages can cause some or all of the ICs on the wafers to malfunction. Such failures in ICs are detected at any of the two testing stages, probe testing or final testing.

In yield analysis for semiconductor manufacturing, it is observed that the primary source that results in loss of yield happens during the wafer fabrication stage, while some of the rest of the loss in yield that appears in later stages can be attributed to the issues related to wafer handling. After repeated analysis of causes for yield loss in the wafer fabrication process, it is found out that the causes can be categorized into following categories as shown in the diagram below.

The two main categories are die yield loss and throughput yield loss. This type of categorization does not take into consideration organized yield problems associated with design errors rather it only focusses on the yield loss issues caused by arbitrary events in the manufacturing process. The term throughput yield loss is defined as the variance between the wafers’ input rate and output rate during the fabrication stage. This difference can be caused because of wafers being rejected due to mishandling of the wafers or the equipment or imperfect processing by the handlers.

Imperfect processing can occur primarily due to equipment malfunctioning and wrong sequencing of wafers. Wafer mishandling by the operators can cause wafer damage and gross errors on the wafers. In modern process of yield management in semiconductor manufacturing throughput yield loss is typically very low as most of the stages are automated and there is very less chance of human errors.

Die yield loss is the calculated value based on the number of the total ICs manufactured that are defective. The conflicts or disturbances causing die yield loss can be further categorized in to two types, namely local and global disturbances. The global disturbances are the ones that affect whole wafers in a way that all or majority of the dies fail the wafer acceptance test (WAT). On the other hand, local disturbances affect only parts of the wafer and the affected area dimensions can be compared with IC features like contacts, transistors etc.

Yield Analysis through Yield Management Software

All of this procedure of semiconductor engineering data analysis can be quite daunting if conducted manually. In this analysis, process engineers are required to compile the wafer test data from several sources and then to add their own analysis too. This practice can take hours or even days. By using yieldWerx Enterprise, which is a complete end-to-end yield management solution, the reporting and data analysis processes becomes automated and can be accomplished within minutes. It offers a very detailed statistical root cause analysis in just a couple of clicks.

It is designed to handle semiconductor manufacturing and engineering data analysis that include all sorts of test data. yieldWerx offers a real-time, comprehensive overview of the whole manufacturing supply chain, making it very easy to classify, examine and act on yield or quality related problems in test and manufacturing processes, helping its customers save on cost and increases productivity.